arterisip provides network-on-chip interconnect ip to soc makers so they can reduce cycle time, increase margins, and easily add functionality. unlike traditional solutions, arteris’ plug-and-play technology is flexible and efficient, allowing designers to optimize for throughput, power, latency and floorplan. using arterisip solves pain for our customers. traditional bus and crossbar interconnect approaches create serious problems for architects, digital and physical designers, and integrators: massive numbers of wires, increased heat and power consumption, failed timing closure, spaghetti-like routing congestion leading to increased die area, and difficulty making changes for derivatives. arterisip noc ip reduces the number of wires down to one half, results in fewer gates, fewer and shorter wires, and a more compact chip floor plan. having the option to configure each connection’s width, and each transaction’s dynamic priority assures meeting latency and bandwidth requirements. and